1. Technical Field
The subject matter described herein relates to digital signal processor (DSP) based serial receivers. In particular, the subject matter described herein relates to DSP-based serial receivers that are required to achieve a relatively low bit error rate (BER).
2. Description of Related Art
DSP-based serial receivers typically have a conventional flash analog-to-digital converter (ADC). While the traditional flash ADC can achieve a low BER requirement (e.g. 10−15) given ample area and power, there are practical limitations on ADC resolution. Since a traditional N-bit flash ADC requires 2N−1 comparators, power and area increase exponentially with the resolution of the ADC.
While alternative types of traditional ADCs, such as pipeline and successive approximation register (SAR), may significantly reduce the number of comparators (and hence power and area), they could not achieve a low BER at high speed. Due to a lower clock rate, an increased number of interleaved alternative ADCs (and hence increased power and area) would be required to achieve low BER at high speed, e.g., a multi-GHz (multi-gigahertz) rate.